Handbook of Multilevel Metallization for Integrated Circuits by Syd R. Wilson, Clarence J. Tracy, John L. Freeman Jr.

By Syd R. Wilson, Clarence J. Tracy, John L. Freeman Jr.

The instruction manual of Multilevel Metallization for built-in Circuits solutions and significant desire by way of pulling jointly in a single quantity an intensive technical precis of every of the most important components that make up a multilevel steel approach. integrated are linked layout, research, fabrics, and production issues. The booklet then serves 3 reasons: It features as an excellent studying instrument for the engineer newly assigned to paintings in metallization; It serves as a reference textual content for any multi level marketing engineer, new or skilled, who needs to refresh their reminiscence. for somebody who desires to extra concentrate on one topical parts, an intensive directory of references has been supplied.

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1, 4) Thus, decreasing the gate length requires shallower junctions to avoid short channel effects. To preserve the integrity of these junctions and the integrity of the contact resistance, the contact metallization must not interact with Si during any of the subsequent heat cycles. , are needed to remove any gate oxide damage due to deposition and reactive sputter etching, to grow AI metal grains to improve electromigration, to process the interlevel dielectrics needed for multilevel metallization and finally, to package the integrated circuit.

Also, the minimum RC is lower because of the reduced metal resistance. 5 v rn METAL THICKNESS 0 75 )rm METAL T H I C K N E S rn 1 0 p ! n METAL THICKNESS b A 10’2 1 I 0 1 I 2 LINEWIDTH (rrn) Figure 4. 0 pm metal pitch. o LINEWIDTH ( r m ) Figure 5. 0 pm metal pitch. The modeling discussed in the previous paragraph is for an interconnect system where the load and driver device resistance and capacitance are not considered. In a real circuit, the device and load capacitances tend to be small relative to the interconnect capacitance, but the device resistance will be quite large relative to the interconnect resistance until the interconnect length is several millimeters or more.

23) These issues are discussed in Chapter 7. AlSi and AlCuSi alloys were used in prior generations. However, as contact dimensions have decreased below 1 pm and barrier layers have been required, there has no longer been a need for Si in the AI alloy. Some companies have left Si in the alloy longer than necessary due to the cost of requalifying a new metal alloy. Other metal alloys have been investigated, but are not widely used. In the future A1 alloys will probably be replaced by Cu as discussed by Wong in Chapter 13.

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